ALIASING-FREE COMPACTION IN TESTING CORES-BASED SYSTEM-ON-CHIP (SOC) USING COMPATIBILITY OF RESPONSE DATA OUTPUTS
Bibliographic record
Abstract
The realization of space-efficient support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. Novel approaches to designing aliasing-free space compaction hardware were recently proposed in the context of testing cores-based system-on-chip (SOC) for single stuck-line faults, extending the well-known concepts of conventional switching theory, specifically those of cover table and frequency ordering commonly utilized in the simplification of switching functions, and of compatibility relation as used in the minimization of incomplete sequential machines, based on optimal generalized sequence mergeability, as developed and utilized by the authors in earlier works. The advantages of these aliasing-free compaction methods over earlier techniques are quite obvious, since zero-aliasing is achieved without any modifications of the module under test (MUT), while keeping the area overhead and signal propagation delay relatively low as contrasted with the conventional parity tree linear compactors. Besides, the approaches could be applied with both deterministic compacted and pseudorandom test patterns. The subject paper, without furnishing details of the different algorithms developed in the implementation of these approaches to designing zero-aliasing space compactors, provides the mathematical basis of selection criteria for merger of an optimal number of outputs of the MUT to achieve maximum compaction ratio in the design, along with some results from simulation experiments conducted on ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits, with simulation programs ATALANTA, FSIM, and HOPE.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.001 | 0.003 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.001 | 0.001 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.001 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".