StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration
Why this work is in the frame
A frame that forgets how it found something cannot be audited. These are the routes that admitted this work.
Bibliographic record
Abstract
Checkpoint-based debugging flows that allow moving the design state between an FPGA and a simulator have recently emerged. These flows combine the speed of hardware execution and the full observability and controllability of HDL simulation. However, they assume the entire system state can be moved to a simulator, limiting them to self-contained systems and precluding their use in network or CPU-attached FPGAs. In this paper, we present StateLink, a co-simulation framework that allows a design-under-test (DUT) running in a simulator to interact with other design elements that reside in hardware. StateLink creates links between DUT interfaces in the HDL simulation and their equivalents in hardware, thereby allowing the DUT to remain connected to and active in the overall hardware system after its state is moved to a simulator. This extends the functionality of checkpoint-based debugging frameworks to designs with external I/Os such as DRAM and Ethernet, and to designs that contain components with no simulation models. It also significantly decreases the simulation time of DUTs that are part of a large system. For example, it speeds up the HDL simulation of designs that interface with DRAM by up to 25 ×. Incorporating StateLink in a design typically adds no timing overhead and a modest hardware area overhead; for example, StateLink adds 916 LUTs to a 32-bit AXI memory-mapped and 1423 LUTs to a 32-bit AXI streaming interface.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.001 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.001 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it