Rapid And Efficient Multi Objective Design Space Exploration Methods In High Level Synthesis Of Computation Intensive Applications

Design Space Exploration (DSE) is an indispensable segment of the High Level Synthesis (HLS) design process. Moreover, the enormous increase in complexity of the recent Very Large Scale Integration (VLSI) circuits has only been possible due to use of advan ced DSE techniquesduring HLS process. This dissertation presents four automated optimization algorithms and methodologies that are capable to handle various multi-objective problems during design space exploration and high level synthesis of computation intensive applications. Algorithmic solutions to four different branches of DSE problems have been proposed in this dissertation viz. a) Solution to power-performance-area/cost trade-off of Digital Signal Processing (DSP) kernels using priority factor process which also includes deriving analytical mathematical model for modern performance parametric frameworks b) Solution to area-performance-power tradeoff/ power-performance-area tradeoff of DSP kernels using hybridization of fuzzy algorithm and vector design space technique with Self-Correction Scheme c) Solution to dual parametric optimization using efficient multi structure genetic algorithm for integrated scheduling and allocation and d) Solution to control step bound static power optimization using power gradient methodology for integrated scheduling and allocation. Some techniques proposed are equipped with pipelined execution time parameter (based on need), in addition to hardware area, power and cost depending on the user’s objective for exploration of a final solution in a short time. In addition to architecture exploration capability, rapid automated circuit generation of DSP kernels is also possible in a short time for verification and synthesis in Field Programmable Gate Array (FPGA) platforms. The proposed exploration approaches are applied to custom data intensive applications application specific processors/custom processors) or standalone Application Specific Integrated Circuits (ASIC’s). Results of the experiments for proposed approaches on all the standard DSP benchmarks have indicated improvements either in terms of exploration runtime, quality of final solution, reduced execution time, power and area or a multiple combination of all factors when compared to recent approaches.

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