(Invited) Plasma Processes for Emerging Silicon-Based MEMS, NEMS and Packaging Applications

Plasma processes are important for emerging silicon-based micro-electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS) and packaging applications. Typically every device has a customised process flow but synergies can be found as most are produced using a 2.5D approach comprising sequential deposition, lithography and etch cycles. Plasma processes are critical in enabling reproducible dry deposition and etch steps during manufacture. Increasingly they are also being adopted in lithography (nanoimprint) and bonding process steps. Plasma processes can be divided into the following broad families: Chemical vapour deposition (CVD) Atomic layer deposition (ALD) Physical vapour deposition (PVD) Etch (physically-driven) Etch (chemically-driven) Surface functionalisation The merits of each plasma technique and their application to emerging devices are discussed. Plasma-enhanced chemical vapour deposition (PECVD) of dielectrics and silicon is widely used to enable lower temperature processes than conventional low pressure CVD. Adjustment of deposition parameters can tune stress, chemical resistance, optical properties and wear characteristics for different application requirements. At higher temperatures, plasma-assisted nanogrowth of carbon nanotubes and 2D materials (e.g. graphene) are emerging technologies. Conversely, inductively coupled plasma CVD (ICP-CVD) is attracting interest to enable high quality films at lower temperatures. Plasma-assisted ALD enables thin and uniform layers to be grown in a wider range of materials and, similarly, high quality films at lower processing temperatures. Plasma-based PVD processes include sputtering and ion beam deposition. The former is a standard technique for metallisation. Al-based schemes are typical in the silicon IC industry but different metallisations (e.g. Au or Pt-based) may be required for sensors to give HF resistance or long lifetime contacts. Ion beam deposition is often used for complex multilayer stacks. Physically-driven etch processes require ions to provide enough energy to enable a chemical reaction or to physically break bonds at the wafer surface. Conversely, chemically-driven etch processes spontaneously react but require passivation species to obtain directionality (anisotropy). Ion beam etch processes enable non-volatile materials to be physically etched, such as Vanadium Oxide for uncooled infra red detectors. If the substrate is tilted then non-vertical structures, such as blazed gratings, may be realised. Plasmas may be used to clean surfaces or to create specific surface conditions for subsequent steps. This may be to passivate them, increase bond strengths at low temperatures or to subsequently functionalise them – e.g. adding hydrophobic self-assembled monolayers (SAMs) in MEMS microphones or for bio-probes in medical devices. The process step common to the majority of MEMS devices today is the Bosch silicon etch. This uses a repeating sequence of PECVD deposition, physical etch for directional passivation removal and chemical etch that results in a high rate, highly vertical and highly selective silicon etch - although the cyclic nature results in a characteristic sidewall roughness (scalloping). High aspect ratio structures may be realised and the process is not sensitive to crystal orientation (which limits geometries with anisotropic wet etchants). The majority of physical sensing devices are based on sub-70μm depth features. Trends are towards higher aspect ratios for enhanced performance and smaller footprint whilst maintaining throughput. Increasingly, large cavities are also being etched for subsequent chip or wafer scale packaging and sensor structures may comprise multi-wafer stacks with one of more having through wafer etches (300-750μm). With the move to multi-wafer structures interconnect becomes more challenging. Monolithically integrated devices are key to some high volume MEMS applications; however, the most common approach is to use hybrid integration – allowing separate optimisation of readout IC and MEMS devices. Increasingly solutions are moving towards system-in-a-package (SiP) and system-on-a-chip (SoC) solutions. Through silicon vias (TSVs) are emerging as a key technology for this in both the MEMS and IC industries. Aspect ratios are generally limited to 10-15:1 using the Bosch process in production. This is typically followed by dielectric isolation (e.g. TEOS) and barrier / seed metal layers (e.g. by ALD) prior to electroplating for a low via resistance. At the nanoscale, etching becomes more challenging. The Bosch process is less well suited due to finite sidewall scallop size and reduced rate / selectivity. Typically it is not used below 500nm feature sizes although 100nm features have been demonstrated. A continuously passivating process has smooth sidewalls but a lower rate, selectivity and aspect ratio capability at room temperature. Moving to cryogenic temperatures enables the highest rate, selectivity and aspect ratios to be achieved and can realise trench features down to 10nm. Emerging applications in silicon-based MEMS, NEMS and packaging require a diverse range of plasma processes. With no standardised process flow, individual tools need the flexibility to address multiple different process requirements and enable unit cost reductions by running multiple products to achieve higher volumes. Figure 1

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