Machine Learning-Driven Flip-Flop Timing Model and its Application in Resolving Marginal Timing Violations

Traditionally, we define a safe operating region for flip-flops using the setup and hold time constraints, with other timing attributes, such as clock-to-Q (C2Q) delay, modelled with the assumption that the flip-flop operates within this region. However, in reality, these constraints and C2Q delay are interdependent, and a conservative approach is taken to define these constraints. Hence, traditional flip-flop models, though safe, hinder optimization and limit overall performance improvement. In this article, we leverage machine learning (ML) techniques to define a safe operating region for a flip-flop, effectively extending the traditional timing space. Specifically, rather than modelling setup and hold times, we develop an ML model that predicts the probability of latching data correctly by a flip-flop. This model considers the overall impact of circuit conditions, such as setup and hold skews, and also accounts for process-induced variations, thus implicitly capturing the dependencies among various parameters missing in the traditional model. Additionally, we propose a second ML-based model to accurately predict the C2Q delay within the extended timing space. Furthermore, we demonstrate the application of these models in resolving marginal timing violations through waivers rather than implementing design modifications. We propose a hierarchical violation waiver framework that enables safely waiving violations. Besides considering latching probability, the violation waiver checks that the timing space extension does not introduce issues for flip-flops that were already operating safely under the timing constraints of the traditional model. We validate the proposed framework on TAU CONTEST’19 benchmark circuits, implemented with 45 nm technology libraries and verified against Monte Carlo SPICE simulations. Results show that marginal violations are effectively filtered with a precision of 100% (i.e., avoiding false positives) and errors in computing C2Q delay are less than 2% compared to the golden SPICE delay computed in the extended timing region.

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