Parallel Synthesis of Large Combinational Circuits for FPGAs
Bibliographic record
Abstract
Abstract High level synthesis tools are the main stream today for the rapid design of electronic circuits. At a lower level, logic synthesis systems like SIS [7] are in charge of the optimization of the combinational part of the circuit. These tools also realize the mapping of the design on programmable devices such as fpgas. The logic synthesis is a computation intensive task. We propose in this paper to partition the graph representing the circuit to reduce the synthesis problem size. Splitting decreases runtime and allows the use of more performant algorithms. However, it leads to a lost of quality for the final circuit. To perform an efficient partitioning, we have adapted an up-to-date algorithm, Metis [9], for the partitioning of circuit graphs. Since subcircuits are processed separatly using SIS, a distributed implementation based on PVM [6] has also been realized. Results are very encouraging for both the runtime and the solution quality of the synthesis on a network of up to 8 workstations. Introduction Electronic circuit cad tools are in charge of converting a description of a digital circuit into an interconnection of logic gates, namely a gate-level net-list (see fig 1).
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How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".