Synthesizing specialized sparse tensor accelerators for reconfigurable hardware using high-level functional abstractions

Sparsity is inherent in many applications such as machine learning and graph analytics.However, achieving high efficiency in sparse computations requires specialized hardware accelerators like FPGAs, as traditional accelerators like CPUs and GPUs typically cater to dense data.While high level synthesis enables the automatic generation of FPGA-based accelerators, generic solutions produced via C-based synthesis flows often demand extensive development time, leading designers to prioritize broad applicability over fine-grained structural specialization.Consequently, these accelerators fail to fully exploit FPGA's reconfigurability, leaving substantial performance and efficiency gains untapped.This thesis pushes the boundary by automatically generating specialized accelerators that match a given fixed sparse-structure (e.g., in static graph analytics and pruned neural networks).It accomplishes this by adapting a functional, type-driven compilation methodology previously shown to be highly effective at producing high-performance GPU code for sparse tensor algebra.By reimagining this approach for reconfigurable hardware, the thesis introduces specialized primitives designed specifically for irregular data.Encoding tensor shapes directly within the type system allows concise specifications of sparse accelerators and facilitates advanced optimizations, such as dynamic partitioning and vector sharding, ultimately generating hardware precisely customized to the sparsity patterns of the underlying tensors.Compared to state-of-the-art generic accelerators (HiSparse, HiSpMV and GraphLily), the approach achieves up to a 2.8× improvement in bandwidth efficiency for sparse matrix i

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