Increasing FPGA CAD Adaptability using Reinforcement Learning and Smart Perturbations

Field-programmable gate arrays (FPGAs) continue to evolve to best exploit the capabilities of new manufacturing technologies and to meet new applications’ needs. Hence, there is a need for an adaptable, high-quality FPGA computer-aided design (CAD) flow that can evaluate new architectural ideas. FPGA CAD tools should also efficiently map complex designs from various applications to completely defined devices in a short runtime to speed up design cycles and increase productivity. This thesis focuses on enhancing the adaptability and efficiency of the open-source VTR CAD flow,with a specific emphasis on the packing and placement stages. As placement is the most time-consuming stage in the FPGA CAD flow, we investigate various techniques to optimize it. First, we propose multiple smart perturbations that relocate blocks during simulated annealing placement to optimize both the wirelength and the critical path delay of the design. Second, we formulate the problem of selecting the move type to use at each point in the anneal as a reinforcement learning problem (introducing RLPlace). Subsequently, RLPlace 2.0 advances this concept by empowering the agent not only to determine the move type but also the specific block type to be moved. This innovation significantly enhances adaptability, allowing the tool to cater to a broader spectrum of FPGA architectures and application domains, while simultaneously improving the quality and the runtime of the flow. Additionally, to allow a more flexible CAD flow, we introduce the re-clustering API that can efficiently modify the packing decisions in various stages throughout the flow. This API opens the door for exploring many ideas like breaking the barrier between packing and placement by enabling more fine-grained moves during placement or building a generic legalizer for semi-legal flat placers. We verify the efficacy of the re-clustering API by implementing a multi-threaded iterative improvement packing algorithm. We also enhance the software engineering of VTR by doing code refactoring, implementing new graphical interfaces and much more. By combining adaptive RL algorithms, APIs to facilitate additional optimization, and a better engineered and flexible software tool, this thesis represents a significant stride towards a more adaptable and efficient FPGA CAD flow.

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