Architecture and CAD Techniques for Efficient FPGA Implementation of Machine Learning and Other Applications
Bibliographic record
Abstract
Field-programmable gate arrays (FPGAs) offer an alternative to application-specific integrated circuits (ASICs) that is attractive in scenarios where flexibility may be required or where chip volumes are not sufficiently high enough to justify the costs of a custom chip. The flexibility of FPGAs offer users the power/performance benefits of a custom hardware implementation, compared to software running on a processor, without committing to one specific design. However, the flexibility can lead to inefficiencies in terms of development time, area, performance, and power. FPGAs are used for a variety of applications and different optimizations can be applied to increase efficiency of FPGA implementations. This thesis considers techniques that can be applied to achieve efficient implementation of machine learning and other applications on an FPGA from the perspectives of architecture and computer-aided design (CAD). We consider the use of a high-level synthesis (HLS) tool to synthesize an accelerator for deep convolutional neural networks (CNNs) on an FPGA. We implement a complete end-to-end system running on an Arria 10 SoC FPGA. The accelerator implements zero-skipping and reduced-precision convolution with minimal impact on accuracy. We evaluate various versions of the accelerator through software changes and tool constraints alone. Then, we propose architecture changes to the carry-chain architecture in FPGAs to improve the resource utilization of binarized CNNs (BNNs). We add additional carry-chain circuitry that propagates sum instead of the carry. We demonstrate that we are able to reduce FPGA resource utilization while keeping the additional circuit area small. Lastly, we propose to re-map some of the look-up-tables (LUTs) to use the existing carry-chain architecture in order to increase performance by adding a post-LUT mapping step to the FPGA CAD flow. Using a subject graph that closely matches the underlying hardware, we are able to select critical paths to take advantage of the existing fast dedicated carry-chain routing.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.001 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.000 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.001 |
| Insufficient payload (model declined to judge) | 0.010 | 0.002 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".