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4,299,418 works, Canadian by any of four routes.

Every filter state is a URL; the URL is the query; the query is citable via /q/⟨hash⟩. The page, the API and the export parse the same parameters.

The current cohort, streamed from the database: every work column, the machine labels, the provisional scores, and the per-row validation status. Exports are capped at 100,000 rows. Mints a permanent /q/ link for this exact query. The same filters always produce the same link, whoever asks.

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Low-power high-performance VLSI design
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Direct Codex and Gemma labels are unvalidated and sparse. Distilled predictions cover the full frame and are also unvalidated. Choose the evidence source explicitly; absence of a direct label is never a negative label.

affaffiliation
fundfunder
venuejournal
aboutaboutness

The four routes compose: require the funder route and exclude affiliation to get the funder-only stratum no affiliation-based frame ever sees.

955 results · 1 filter active ·
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20002025
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Machine labels · sparse coverage
Evidence
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An unlabeled work is unknown, not a negative. Label coverage is reported on every query.
955 works in the cohort · of 4,299,418page 2 of 20

Labels cover 2 of 955 works in this cohort. The rest are unlabeled, which is not a negative label: the label table is sparse today and grows as labeling rounds land.

Distilled predictions cover 955 of 955 works in this cohort. Predictions are machine_predicted_unvalidated. The Gemma side is a direct model label for every work (title-only); the Codex side is a distilled, calibrated classifier. Candidate is the union; consensus is the intersection.

affunlabeled
A low-power reduced swing global clocking methodology
Farhad Haj Ali Asgari, Manoj Sachdev
2004· article· en· IEEE Transactions on Very Large Scale Integration (VLSI) Systems· Engineering
machine prediction:candidate · noneconsensus · none
50
citations
affunlabeled
Analysis and Design of On-Chip Decoupling Capacitors
Tasreen Charania, A. Opal, Manoj Sachdev
2012· article· en· IEEE Transactions on Very Large Scale Integration (VLSI) Systems· Engineering
machine prediction:candidate · noneconsensus · none
41
citations
affunlabeled
FPGA clock network architecture
Julien Lamoureux, Steven J. E. Wilton
2006· article· en· Engineering
machine prediction:candidate · noneconsensus · none
41
citations
venueno affunlabeled
New improved 1-bit full adder cells
Sreehari Veeramachaneni, M.B. Srinivas
2008· article· en· Conference proceedings - Canadian Conference on Electrical and Computer Engineering· Engineering
machine prediction:candidate · noneconsensus · none
39
citations
affunlabeled
Multiple-valued logic in FPGAs
Z.G. Vranesic
2002· article· en· Engineering
machine prediction:candidate · noneconsensus · none
38
citations
afffundunlabeled
A New Single-Ended SRAM Cell With Write-Assist
Richard F. Hobson
2007· article· en· IEEE Transactions on Very Large Scale Integration (VLSI) Systems· Engineering
machine prediction:candidate · noneconsensus · none
38
citations
affunlabeled
Clock-Aware Placement for FPGAs
Julien Lamoureux, Steven J. E. Wilton
2007· article· en· Engineering
machine prediction:candidate · noneconsensus · none
36
citations
affunlabeled
Multigrid-like technique for power grid analysis
Joseph Kozhaya, Sani Nassif, Farid N. Najm
2001· article· en· International Conference on Computer Aided Design· Engineering
machine prediction:candidate · noneconsensus · none
33
citations
affunlabeled
An Energy-Efficient Offset-Cancelling Sense Amplifier
Jaspal Singh Shah, David Nairn, Manoj Sachdev
2013· article· en· IEEE Transactions on Circuits & Systems II Express Briefs· Engineering
machine prediction:candidate · noneconsensus · none
31
citations

How this was built: Screen · Findings · About