Notice bibliographique
Résumé
A straightforward relationship between signal-to-noise ration (SNR) and power consumption in CMOS inverters has been developed at the University of Toronto. It indicates that the fundamental limits in time-domain signal processing are set by transistor threshold and supply voltage, rather than technology-scaling, or the approach used to process the signals. Time to digital converter: CMOS inverters are used as delay elements to resolve pico-second time difference between two events CMOS is among the most important technologies used in integrated circuits. Its use spans from digital processors to analogue front-ends for both wireless and wireline communications. CMOS inverters are the simplest CMOS digital elements. They can be used for logic operations, or as a delay element, or even as an analogue voltage amplifier. There is great interest in making inverters faster and less power hungry, as this has a direct impact in on the power dissipation of almost all our everyday electronic devices, such as mobile phones and laptops. CMOS technology is used so widely because of its very low cost compared to alternative IC technologies, as well as its low power dissipation when used for digital operations. The CMOS inverter structure is composed of two types of transistor (n-type and p-type). When the transistors operate as switches, the structure works like a digital element whose output is the inverse (or complement) of the input. As a digital element, the inverter can also be used as a delay stage, one of the most important building blocks for circuits based on time-domain signal processing. When the transistors operate as voltage-to current amplifiers, the structure acts as an inverting voltage amplifier, producing an amplified replica of the input signal with opposite phase. “The CMOS inverter is only one of the numerous structures that can be created with CMOS technology,” said Toronto team member Dr Antonio Liscidini. “However, the study of the limits of performance of the CMOS inverter can be useful to understand the overall limitations of such technology and what benefit an evolution of CMOS technology could realise.” At the end of the last century Enz and Vittot demonstrated that there is a precise correlation between the signal-to-noise ratio achievable by the CMOS structure when used as an amplifier, and the power dissipated. “Such limit, evaluated only for the CMOS amplifier was found to be the same for even more complex circuits, such as analogue-to-digital converters and switched capacitors filters,” Liscidini explained. “Our aim was to analyse the performance of the CMOS inverter used as a delay element, to find a straightforward relationship between signal-to-noise ratio and power consumption'. Like the one found by Enz and Vittot for voltage mode operation”. In their Letter the Toronto researchers report their success in this respect, but also go on to demonstrate that regardless of the mode of operation, the fundamental limit is substantially the same. In time-domain signal processing this limit does not improve with technology scaling, but is mainly dominated by the ratio between the transistor thresholds and the voltage supply adopted. “The importance of this result,” said Lisicidini, “is that, despite the approach chosen to process the signals (voltage-domain or time-domain), similar boundaries will be found. Regardless of technology scaling, time-domain signal processing cannot offer a privileged path to reach lower power consumption for a targeted signal-to-noise ratio.” Dr Antonio Liscidini at the University of Toronto The authors also hope this understanding of the fundamental limitations will also be useful in comparing different designs based on time-domain signal processing; offering an additional instrument to highlight the benefits of the different techniques adopted in literature.
Récupéré en direct depuis OpenAlex et désinversé. Les résumés ne sont pas conservés dans cette base de données : les index inversés représentent 8,6 Go des 9,3 Go de texte de la base, et le serveur dispose de 13 Go libres.
Comment cette classification a été obtenuedéplier
Prédiction distillée sur la base complète
Imitation des enseignantsNi prévalence calibrée, ni vérité terrain. Validation humaine à venir. Apprise à partir de 10 348 étiquettes directes de Codex et de 10 348 étiquettes directes de Gemma. Le mode candidate est l'union des têtes enseignantes seuillées; le consensus est leur intersection. Ces sorties portent le statut machine_predicted_unvalidated et ne sont ni des étiquettes humaines ni des étiquettes directes de modèles de pointe.
Scores Codex et Gemma par catégorie
| Catégorie | Codex | Gemma |
|---|---|---|
| Métarecherche | 0,000 | 0,000 |
| Méta-épidémiologie (sens strict) | 0,000 | 0,000 |
| Méta-épidémiologie (sens large) | 0,000 | 0,000 |
| Bibliométrie | 0,000 | 0,000 |
| Études des sciences et des technologies | 0,000 | 0,000 |
| Communication savante | 0,000 | 0,000 |
| Science ouverte | 0,000 | 0,000 |
| Intégrité de la recherche | 0,000 | 0,000 |
| Charge utile insuffisante (le modèle a refusé de juger) | 0,000 | 0,000 |
Scores machine (provisoires)
Les deux têtes enseignantes du modèle étudiant, lues sur ce travail. Un score ordonne la base pour la relecture; il n'affirme jamais une catégorie, et le statut de validation accompagne chaque rangée tel quel.
Scores de référence d'un modèle non mature (critères de maturité non atteints, 7 itérations). Un score ordonne; il n'affirme jamais une catégorie.
score_only:v0-immature-baseline · tel quel depuis la passe de notation : score_only signifie que le nombre peut ordonner les travaux, et qu'aucune étiquette de catégorie n'en découleClassification
machine, non validéePrédiction automatique; un appel candidat d’une seule tête enseignante, pas un consensus.
Le détail, modèle par modèle et score par score, se trouve en fin de page sous « Comment cette classification a été obtenue ».