noise limiting

A straightforward relationship between signal-to-noise ration (SNR) and power consumption in CMOS inverters has been developed at the University of Toronto. It indicates that the fundamental limits in time-domain signal processing are set by transistor threshold and supply voltage, rather than technology-scaling, or the approach used to process the signals. Time to digital converter: CMOS inverters are used as delay elements to resolve pico-second time difference between two events CMOS is among the most important technologies used in integrated circuits. Its use spans from digital processors to analogue front-ends for both wireless and wireline communications. CMOS inverters are the simplest CMOS digital elements. They can be used for logic operations, or as a delay element, or even as an analogue voltage amplifier. There is great interest in making inverters faster and less power hungry, as this has a direct impact in on the power dissipation of almost all our everyday electronic devices, such as mobile phones and laptops. CMOS technology is used so widely because of its very low cost compared to alternative IC technologies, as well as its low power dissipation when used for digital operations. The CMOS inverter structure is composed of two types of transistor (n-type and p-type). When the transistors operate as switches, the structure works like a digital element whose output is the inverse (or complement) of the input. As a digital element, the inverter can also be used as a delay stage, one of the most important building blocks for circuits based on time-domain signal processing. When the transistors operate as voltage-to current amplifiers, the structure acts as an inverting voltage amplifier, producing an amplified replica of the input signal with opposite phase. “The CMOS inverter is only one of the numerous structures that can be created with CMOS technology,” said Toronto team member Dr Antonio Liscidini. “However, the study of the limits of performance of the CMOS inverter can be useful to understand the overall limitations of such technology and what benefit an evolution of CMOS technology could realise.” At the end of the last century Enz and Vittot demonstrated that there is a precise correlation between the signal-to-noise ratio achievable by the CMOS structure when used as an amplifier, and the power dissipated. “Such limit, evaluated only for the CMOS amplifier was found to be the same for even more complex circuits, such as analogue-to-digital converters and switched capacitors filters,” Liscidini explained. “Our aim was to analyse the performance of the CMOS inverter used as a delay element, to find a straightforward relationship between signal-to-noise ratio and power consumption'. Like the one found by Enz and Vittot for voltage mode operation”. In their Letter the Toronto researchers report their success in this respect, but also go on to demonstrate that regardless of the mode of operation, the fundamental limit is substantially the same. In time-domain signal processing this limit does not improve with technology scaling, but is mainly dominated by the ratio between the transistor thresholds and the voltage supply adopted. “The importance of this result,” said Lisicidini, “is that, despite the approach chosen to process the signals (voltage-domain or time-domain), similar boundaries will be found. Regardless of technology scaling, time-domain signal processing cannot offer a privileged path to reach lower power consumption for a targeted signal-to-noise ratio.” Dr Antonio Liscidini at the University of Toronto The authors also hope this understanding of the fundamental limitations will also be useful in comparing different designs based on time-domain signal processing; offering an additional instrument to highlight the benefits of the different techniques adopted in literature.

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