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Record W179156617

SRAM in Three Dimensional Integrated Circuits

2009· article· en· W179156617 on OpenAlexfundno aff
Negin Golshani

Bibliographic record

VenueResearch Repository (Delft University of Technology) · 2009
Typearticle
Languageen
FieldEngineering
Topic3D IC and TSV technologies
Canadian institutionsnot available
FundersUniversity of TorontoTechnische Universiteit Delft
KeywordsStatic random-access memoryElectronic circuitIntegrated circuitElectronic engineeringComputer scienceProcess (computing)Process variationSense amplifierElectrical engineeringEngineeringSemiconductor memory
DOInot available

Abstract

fetched live from OpenAlex

In most of the electronics and communication devices such as mobile, video phone and handheld video games low power and high density SRAM (Static Random Access Memory) is a favor. On the other hand, integration of many functions such as digital, memory, RF and analog circuits is necessary in near future. Scaling is one of the solutions to increase density of memories and functionality of integrated circuits. However, the increase of leakage current, process complexity and process variation of parameters limit scaling. This limitations force us to think about new dimension in integrated circuits. Three dimensional integrated circuits can solve some of the problems. They can give us low power, high density memories and high functionality circuits in same area of planar ICs. Different technologies can be merged in different layers of 3DIC to finally make a high performance system. In this thesis we realize SRAM cells in 3DIC to increase the capacity and performance of them. In chapter 2 we will introduce different memories and particular case SRAM. The principle of operation and design metrics are discussed in this chapter. Then in chapter 3 we talk about 3DIC and its advantages and disadvantages. Heat generation is main issue in 3DIC. New 3DIC fabrication technology called µ-Czochralski Process is introduced. Next in chapter 4 we design SRAM cells using analytic approach and we confirm the design by circuit simulation tools. Different SRAM cells and sense amplifier and output buffers are designed in this chapter. To fabricate design circuits we need layout for SRAM cells. In chapter 5 we extensively look to the design rules for SRAM circuits in one layer and two layers of silicon. Using double gate and H-Gate transistors to increase the performance of SRAM cells are discussed in this chapter. Then in chapter 6 we show fabrication process flow of one layer and two layers single grain silicon devices. Finally fabricated circuits are characterized electrically and results are reported in chapter 7.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Bench or experimental · Consensus signal: Bench or experimental
GenreCandidate signal: Empirical · Consensus signal: Empirical
Teacher disagreement score0.289
Threshold uncertainty score0.547

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0010.001
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0010.000
Research integrity0.0000.001
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.021
GPT teacher head0.238
Teacher spread0.217 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one teacher head, not a consensus.

The models applied no category: nothing in the taxonomy fit this work.
Study designBench or experimental
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations0
Published2009
Admission routes1
Has abstractyes

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