MétaCan
Menu
Back to cohort
Record W1912648079 · doi:10.1109/newcas.2004.1359046

A worst-case circuit delay verification technique considerino power grid voltage variations

2004· article· en· W1912648079 on OpenAlexaff
D. Kouroussis, Rubil Ahmadi, Farid N. Najm

Bibliographic record

VenueThe 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004. · 2004
Typearticle
Languageen
FieldEngineering
TopicLow-power high-performance VLSI design
Canadian institutionsUniversity of Toronto
Fundersnot available
KeywordsStatic timing analysisComputer scienceBenchmark (surveying)Delay calculationVery-large-scale integrationLogic gateProcess (computing)Power (physics)Electronic engineeringCircuit extractionPhysical designAsynchronous circuitCircuit designElectronic circuitVoltagePropagation delayEquivalent circuitAlgorithmElectrical engineeringSynchronous circuitEngineeringEmbedded systemClock signal

Abstract

fetched live from OpenAlex

In the verification of VLSI circuit design, static timing analysis (STA) techniques allow a designer to calculate the timing of a circuit at different process corners, which only consider cases where all the supplies are low or high. This analysis may not be the true maximum delay of a circuit due to the neglect of mismatch between drivers and load. We propose a new methodology for timing analysis where we identify all the possible critical paths of a circuit using new timing models while integrating the aforementioned mismatch for the logic gates. Given then these critical paths we tie the supplies of the gates to physical power grids and re-analyze for the worst-case time delay. This re-analysis is posed as a sequence of optimization problems where the complete operation of the entire circuit is abstracted in terms of current constraints. We present our technique and report on the implementation results using benchmark circuits tied to a number of test-case power grids.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.001
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesMeta-epidemiology (narrow)
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Simulation or modeling · Consensus signal: none
GenreCandidate signal: Empirical · Consensus signal: none
Teacher disagreement score0.760
Threshold uncertainty score1.000

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0010.000
Meta-epidemiology (narrow)0.0010.001
Meta-epidemiology (broad)0.0010.000
Bibliometrics0.0000.001
Science and technology studies0.0010.000
Scholarly communication0.0000.001
Open science0.0000.000
Research integrity0.0000.001
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.024
GPT teacher head0.232
Teacher spread0.208 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one teacher head, not a consensus.

Study designSimulation or modeling
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations0
Published2004
Admission routes1
Has abstractyes

Explore more

Same venueThe 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.Same topicLow-power high-performance VLSI designFrench-language works237,207