An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI
Bibliographic record
Abstract
Dynamic Voltage Scaling (DVS) is a successful design solution that addresses the challenges associated with low-power/energy and high-performance design in Deep Sub Micron (DSM) CMOS. In DSM, VLSI systems have become interconnect-centric; correspondingly, the associated design solutions should be adapted to preserve their functionality. In reference to this concern, and with respect to DVS, we propose a DVS scheme that takes interconnect effects into account. The proposed DVS scheme is a generalization of existing methods that treat systems as pure logic. To support this DVS scheme, two design metrics are introduced. These metrics model the performance of system components subject to DVS, based on the proportion of their delay due to interconnects. Based on the proposed design metrics, a compact delay model and a method for supply voltage selection are proposed. The limit of scaling for hazard-free system operation in VLSI systems is further formulated. It is shown that this limit can be smaller than the one dictated by the process technology. The proposed DVS scheme is applied to a 4-section global clock distribution network. Reported results show that this scheme improves both the timing accuracy and energy consumption aspects of DVS by 25% and 30% on average, respectively.
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How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.001 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".