Reducing the Instruction Queue Leakage Power in Superscalar Processors
Bibliographic record
Abstract
Today's high performance processors operate in the GHz frequency range and dissipate approximately 100 W of power. According to Moore's Law, in the next generation of microprocessors we expect an exponential increase in the total dissipated power. CMOS technology scaling has been the primary factor responsible for the increase in processor performance. A smaller feature size enables designers to increase the clock frequency and transistor count which significantly affects the processor performance. The drawback of such technology scaling is the leakage power dissipation. As the semiconductor technology scales down, the leakage (standby) power also increases exponentially and accounts for an increasing share of a processor's total power dissipation. This issue becomes a serious problem in mobile hardware where applications may generate long periods of inactivity. In this paper we take a step towards reducing the leakage power dissipation of the instruction queue which allows the out of order execution in a superscalar processor. This unit is responsible for up to 27% of total chip power dissipation in typical superscalar microprocessors. In particular, we reduce the leakage power in the thousands of comparator units in the instruction queue by applying a power gating technique. We rely on detecting the idle time in all comparators. We show that the comparators in the instruction queue stay idle for typically 50% of the total program execution time. This figure is based on the observation that the whole processor pipeline approaches an idle state when a combination of instruction and data cache misses occur. When such idle time is detected we apply power gating to turn off all the comparator units thereby eliminating the leakage power. Our results show that by power gating the comparators using our idle time detecting algorithm it is possible to reduce their leakage power dissipation by up to 95%
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How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.001 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.000 | 0.000 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".