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Record W2096237386 · doi:10.24908/pceea.v0i0.4877

A DATACOMM LABORATORY WITH FPGAS IN A MICROPROCESSOR INTERFACING COURSE

2013· article· en· W2096237386 on OpenAlexaffvenueabout
Jesus David Terrazas Gonzalez, Mohamed Nasri, Tong Duan, Witold Kinsner

Bibliographic record

VenueProceedings of the Canadian Engineering Education Association (CEEA) · 2013
Typearticle
Languageen
FieldEngineering
TopicExperimental Learning in Engineering
Canadian institutionsUniversity of ManitobaPolytechnique Montréal
Fundersnot available
KeywordsInterfacingMicroprocessorComputer scienceMicrocontrollerEmbedded systemField-programmable gate arrayComputer hardwareSoftwareWirelessTelecommunicationsOperating system

Abstract

fetched live from OpenAlex

Teaching undergraduate students about interfacing of microprocessors and microcontrollers in real-time systems is challenging because the circuits have moved from medium to increasingly higher frequencies (multimega- and giga hertz), while wired interfacing has been augmented with wireless interfacing. The trend to design reliable and small-footprint complex digital subsystems also calls for field programmable gate arras (FPGAs). This paper describes an attempt to accommodate the changes through a development of a new FPGA-based lab in an undergraduate course called Microprocessor Interfacing (μI) that has been offered at the University of Manitoba for many years now [1-4]. The course presents real-time wired and wireless interfacing of microcontrollers, microprocessors, and microcomputers to the external world, including interfacing of input/output (I/O) devices with minimum hardware and software, as well as data acquisition with and without microprocessors, data communications, transmission and logging with embedded computers. The following topics are covered: (i) introduction on computing, architectures, processors, and technologies, (ii) architecture and organization of small computer buses, and synchronization of data transfers on local buses (iii) digital input and output (I/O), (iv) digital-to-analog (D/A) and analog-to-digital (A/D) signal conversions and converters, (v) and interfacing aspects in data communications, including encoding, modulation, error detection and forward error protection. The course also includes (a) demonstrations of bus architectures, modules, systems, and new devices, as well as (b) updates on new concepts, technologies, protocols, and software. The laboratories are innovative in terms of three levels of complexity: the Tier1 level includes five 3-hour standard labs designed for all students, the Tier2 is designed for more experienced students, and the Tier3 level lab is designed as a project for groups of students with demonstrated prior design and implementation experience [3]. This paper describes a new laboratory in this course designed to show how to achieve asynchronous data communications using both VLSI components and field programmable gate arrays (FPGA). The first embodiment is designed to illustrate the principles of operation, while the second is to demonstrate how complex functional subsystems can be implemented in FPGA reconfigurable hardware. The laboratory has been used in the course, and produced encouraging results.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame distilled prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: codex-gemma-dda1882f352aValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Observational · Consensus signal: Observational
GenreCandidate signal: Empirical · Consensus signal: Empirical
Teacher disagreement score0.189
Threshold uncertainty score0.802

Codex and Gemma teacher scores by category

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.001
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0000.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0000.000

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.002
GPT teacher head0.169
Teacher spread0.167 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one teacher head, not a consensus.

The models applied no category: nothing in the taxonomy fit this work.
Study designObservational
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations0
Published2013
Admission routes3
Has abstractyes

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