Structured Logic Arrays for Future CMOS Technologies
Bibliographic record
Abstract
As we continue to scale the dimensions of transistors and wires in the deep submicron (DSM) era, the resolution of photolithographic processes is quickly reaching its limits and causing problems in the reliable manufacture of integrated circuits. The design methods using standard cell ASICs (SC-ASIC) produce randomly placed gates and interconnects which are difficult to fabricate at fine geometries, such as 65 nm and below. Besides reduced yield, they also suffer from high testing cost, even with the most advanced built-in self-test methods. These shortfalls motivated us to search for more structured logic architectures for future technologies that can be fabricated more easily and are better suited to self-test, and eventually self-repair. In this paper, we focus on programmable logic arrays to explore their potential when competing for speed, area and power with SC-ASIC. We will investigate the critical path delay for clock-delayed PLAs and provide equations for quick estimation of capacitive loads, delays and areas using technology-independent parameters. These equations can be used in front-end CAD tools for partitioning and architecture decision-making before the logic is implemented in a specific technology. We analyse the PLA to determine optimal sizes for logic implementation. We find that circuits with higher than 200 product terms have slower PLA implementations than SC-ASIC. They often take more than 10 times the area of SC-ASIC designs. To overcome these problems, we introduce methods to subdivide the slower PLAs in order to improve the overall circuit timing and area. For example, by dividing a circuit into two PLAs, we can cut its delay by half and keep the increase in area minimal.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.002 |
| Open science | 0.001 | 0.001 |
| Research integrity | 0.001 | 0.001 |
| Insufficient payload (model declined to judge) | 0.018 | 0.005 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".