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Record W2109804124 · doi:10.1109/inm.2015.7140448

Demonstration of an FPGA controller for guaranteed-rate optical packet switching

2015· article· en· W2109804124 on OpenAlexaff
Maryam Rezaee, Ted H. Szymanski

Bibliographic record

Venuenot available
Typearticle
Languageen
FieldComputer Science
TopicSoftware-Defined Networks and 5G
Canadian institutionsMcMaster University
Fundersnot available
KeywordsComputer scienceComputer networkForwarding planeTestbedNetwork packetMultiprotocol Label SwitchingField-programmable gate arrayPacket switchingNetwork switchLabel switchingOpenFlowQueueing theorySoftware-defined networkingEmbedded systemQuality of service

Abstract

fetched live from OpenAlex

A switch controller which achieves low-latency deterministic `Guaranteed-Rate' (GR) connections in packet switched networks is demonstrated on a `Field Programmable Gate Array' (FPGA) device. A Software Defined Networking (SDN) control plane can configure the FPGA controllers to establish deterministic GR connections in a forwarding plane of IP routers or layer-2 packet switches. The use of deterministic GR connections can reduce queueing delays to negligible values, so that the end-to-end delays are reduced to the fiber latency. The switch controller can operate routers, switches and links at 100% loads, while simultaneously guaranteeing very low end-to-end queueing delays. A testbed consisting of 8 switches in a linear array is synthesized on an Altera Cyclone IV FPGA. An SDN control plane routes 128 traffic flows through the testbed to saturate the switches and links. Packets move through the forwarding plane at a clock rate of 52 MHz, transferring millions of packets per second, and statistics are recorded. The demonstration shows that all traffic flows in the testbed achieve deterministic GR service. The FPGA demonstration is accompanied by a video which visually illustrates packet forwarding in the network. The GR technology applies to IP routers and layer 2 packet switched networks, with thousands of nodes spanning arbitrary distances. The FPGA controller also applies to layer 2 MPLS (Multiprotocol Label Switching) and Ethernet switches, and to `Optical Packet Switched' networks, to achieve deterministic GR services and to operate links at 100% loads.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame machine prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.000
Version: metacan-v3-hybrid-931329e0061cValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Bench or experimental · Consensus signal: Bench or experimental
GenreCandidate signal: Empirical · Consensus signal: Empirical
Teacher disagreement score0.004
Threshold uncertainty score0.014

Distilled classifier scores by category (both heads)

CategoryCodexGemma
Metaresearch0.0000.000
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.000
Science and technology studies0.0000.000
Scholarly communication0.0000.000
Open science0.0010.000
Research integrity0.0000.000
Insufficient payload (model declined to judge)0.0040.001

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.038
GPT teacher head0.274
Teacher spread0.236 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.

The models applied no category: nothing in the taxonomy fit this work.
Study designBench or experimental
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations3
Published2015
Admission routes1
Has abstractyes

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