A Thread Specific Load Balancing Technique for a Clustered SMT Architecture
Bibliographic record
Abstract
Clustering an architecture enables hardware to operate at high clock frequencies by grouping resources into small clusters. This allows local communication within a cluster to travel shorter distances at the cost of an increased number of communications and longer inter-cluster communication latencies. Simultaneous multi-threaded architectures (SMT) allow better utilization of resources, thus a clustered SMT architecture exploits the advantages of SMT architectures and hides much of the inter-cluster communication latencies incurred due to clustering. This is achieved by executing instructions from a different thread when a thread stalls waiting for inter-cluster communication. In this work we study a new load balancing technique for an SMT clustered architecture namely, thread specific load balancing (TSLB). Unlike previous load balancing techniques that balance the load across clusters based on the total number of instructions of all threads in each cluster, TSLB allows each thread to balance its load between clusters independently. With this policy queues can take advantage of the inherent parallelism between instructions from the different threads. In previous load balancing techniques the overall number of instructions from the same thread assigned to distant clusters can be considerable, and if so, will result in high number of inter-cluster communications. In contrast, TSLB maintains an almost constant average number of inter-cluster communications due to the even distribution of instructions between clusters. We have assigned a number to each thread in each cluster that indicates the maximum number of instructions that can be executed to the specified cluster from that thread; these numbers are initially all equal but will vary with time depending on the workload of each thread. This decreases the potential queue conflicts in larger threads thus allowing them to execute faster.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.001 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.001 | 0.001 |
| Science and technology studies | 0.001 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.001 | 0.000 |
| Research integrity | 0.000 | 0.001 |
| Insufficient payload (model declined to judge) | 0.002 | 0.001 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".