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Record W2335460835 · doi:10.1115/ipack2013-73202

A Hierarchical Framework for Thermal Modelling of Electronic Devices: From Atoms to Chips

2013· article· en· W2335460835 on OpenAlexafffund
David A. Romero, Elham Pakseresht, Daniel P. Sellan, Aydin Nabovati, Cristina H. Amon

Bibliographic record

Venuenot available
Typearticle
Languageen
FieldMaterials Science
TopicThermal properties of materials
Canadian institutionsUniversity of Toronto
FundersNatural Sciences and Engineering Research Council of CanadaAdvanced Micro Devices
KeywordsPhononThermal conductivitySiliconBoltzmann equationMaterials scienceLogic gateTransistorThermalElectronic engineeringStatistical physicsOptoelectronicsPhysicsCondensed matter physicsEngineeringThermodynamicsQuantum mechanicsVoltage

Abstract

fetched live from OpenAlex

In this work, we provide an overview of a hierarchical computational framework to predict thermal transport in electronic devices through integration of physics-based models at different length scales. Information from atomistic simulations at the smallest length scales are transferred to upper levels of the hierarchy, up to thermal models for the chip. The proposed methodology includes five levels of length scales in electronic devices, namely (i) atomistic level, (ii) thin film and nanowire level, (iii) transistor and logic gate level, (iv) functional block level, and (v) chip level. At the first level of the hierarchy, properties of energy carriers in a semiconductor material (e.g., phonons) are obtained from atomistic level simulations, such as Molecular Dynamics (MD) and Lattice Dynamics (LD) calculations. At the second level, thermal transport in thin silicon films is modelled using a Lattice Boltzmann Method (LBM) for phonons. The outcome of these simulations is a size-dependent thermal conductivity for silicon films. At the third level of the hierarchy, these effective thermal conductivities are used in thermal modelling of logic gates. Detailed structures of different types of logic gates are reconstructed based on different manufacturing technologies (MOSFET and FinFET) at different technology nodes. Since the characteristic sizes of different parts of the logic gates are comparable to the mean free path of energy carriers, we use the size-dependent, effective thermal conductivities that were calculated at lower levels of the hierarchy to build simulation models for the logic gates. Based on these models, we calculate an equivalent thermal conductance for the logic gates, which would then be used in the upper level simulations to determine an equivalent thermal conductance for different functional blocks of the die based on their internal structure and the number and type of logic gates found in each functional block. Overall, the proposed hierarchical model enables us to include the effect of atomistic-level physics into package-level simulations, and thus, have an accurate prediction of thermal transport in an electronic device.

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame machine prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.

metaresearch head score (Codex)0.001
metaresearch head score (Gemma)0.002
Version: metacan-v3-hybrid-931329e0061cValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Simulation or modeling · Consensus signal: Simulation or modeling
GenreCandidate signal: Empirical · Consensus signal: none
Teacher disagreement score0.010
Threshold uncertainty score0.019

Distilled classifier scores by category (both heads)

CategoryCodexGemma
Metaresearch0.0010.002
Meta-epidemiology (narrow)0.0010.001
Meta-epidemiology (broad)0.0010.002
Bibliometrics0.0010.001
Science and technology studies0.0010.002
Scholarly communication0.0020.002
Open science0.0030.002
Research integrity0.0020.002
Insufficient payload (model declined to judge)0.0030.001

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.036
GPT teacher head0.249
Teacher spread0.213 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.

The models applied no category: nothing in the taxonomy fit this work.
Study designSimulation or modeling
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations0
Published2013
Admission routes2
Has abstractyes

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