Power and Area Efficient Sub-threshold 6T SRAM with Horizontal Local Bit-Lines and Bit-Interleaving
Bibliographic record
Abstract
SRAM in the typical microprocessor consumes a substantial amount of on-chip area and significantly contributes to static power dissipation.Previous studies have shown that sub-threshold operation presents a minimum energy point that is optimal if ultralow power consumption is desired.However, the standard 6T SRAM cell does not operate at sub-threshold voltages.Instead, designs with higher transistor counts are typically used for sub-threshold operation.These designs generally have low integration density.This study presents a new SRAM architecture with minimum area that utilizes a modified 6T SRAM cell for sub-and near-threshold operation in ultra-low power applications.This new architecture introduces horizontal bit-lines, mitigates halfselect disturb, and supports bit-interleaving.The proposed design's stability was thoroughly tested in the presence of process, temperature, and voltage variations, and compared to the standard 6T and traditional 8T cells.A 32kb SRAM block implementing the proposed architecture was designed, simulated, and contrasted to a traditional 8T SRAM cell block.The simulated 32kb SRAM block operates at a maximum frequency of 544.8 khz and 6.70 Mhz for the read and write operations, respectively, and consumes 0.586 pJ/bit in the read operation and 0.17 pJ/bit in the write operation.A very similar 32kb SRAM block consisting of the traditional 8T SRAM cell was found to have a maximum frequency of 544.8 kHz and 2.89 Mhz for the read and write operations, respectively, and consumes 0.736 pJ/bit in the read operation and 0.205 pJ/bit in the write operation.The results show that the proposed design has lower power consumption than the 8T SRAM block, comparable read performance, and better write performance.This was all achieved while only having a 10% increase in area per bit over the conventional 6T thin-cell layout. I would like to thankProfessor Maitham Shams, my thesis supervisor, for accepting me as a graduate student, his support, and guidance.Professor Dimitrios Makrakis
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.002 | 0.001 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".