Analog and mixed-signal test methods using on-chip embedded test cores

A robust method has been developed for the test and characterization of analog and mixed-signal integrated circuits. The method relies on a compact, robust, and easily synthesized integrated test core capable of emulating the function of external automatic test equipment. The core consists of a 2 x N memory whose contents are periodically circulated, a coarse analog filter, and a voltage comparator. One half of the circular memory is used to generate analog signals without the need for multi-bit digital-to-analog converters. The second half is used to generate extremely accurate DC levels, the latter being programmed using a clever software encoding technique that relies on some form of sigma-delta modulation. The DC levels, in combination with the comparator, enable multi-bit digitization using a progressive multiple conversion pass procedure. In order to accommodate broadband circuit phenomena, a delayed-clock sub-sampling mechanism is also employed, in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. One method of delaying the clock is to use a voltage-controlled delay line tuned by a delay-locked loop. The timing resolution of this approach is determined by the value of the consistent clock delay and not its period. A divide-and-conquer approach to the test of deeply embedded analog integrated circuits using the proposed test core is described. Multiple test configurations are presented that can span a wide range of phenomena to be tested both internally to the integrated circuit and externally through I/O interfaces. The applicability of these configurations to increasing test parallelism both at the core and die levels is investigated. Performance limits of the proposed test core are also derived by drawing a comparison to conventional circuits used for data-conversion applications. The same fundamental limitations on integrated circuit performance are shown to affect the test core electronics, although test-specific requirements, such as forcing periodicity and the reliance on software signal processing, help further enhance on-chip measurement accuracy and repeatability. Finally, several successful experimental prototypes that demonstrate the viability of the proposed approach are presented. The prototypes range from concept proving test core integrated circuits to ones containing multiple simultaneously operated test cores and completely embedded circuits under test. In total, several hundred different test cores have been demonstrated, which is further testimony to the practicality of the proposed techniques.

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