Integration Challenges of Flash Lamp Annealed LTPS for High Performance CMOS TFTs

The development of low-temperature polycrystalline silicon (LTPS) based on excimer laser annealing (ELA) has realized CMOS TFTs with notable electrical performance. The flat-panel display industry is searching for alternative LTPS strategies which are cost-effective and easily scalable to large glass panel production, which has led to recent interest in the application of flash-lamp annealing (FLA) for the LTPS crystallization process. The FLA-LTPS process exposes large areas of amorphous silicon with high irradiance from xenon flashlamps for pulse durations that are in microsecond timescale. Amorphous silicon absorbs a sufficient portion of the xenon emission spectrum to melt and crystallize into polysilicon while staying within the thermal constraints of the underlying glass substrate. Multi-lamp exposure systems with high repetition pulse rates would potentially offer significant advantages in manufacturing throughput and cost. The application of FLA-LTPS for CMOS TFTs has been recently reported, with best-case performance comparable to ELA-LTPS. Investigations to improve upon this technology are in progress to address integration challenges to reduce variation in device operation and enable device scaling. The focus areas of this work are material uniformity, source/drain dopant activation, and defect passivation; all of which are fundamental issues facing FLA-LTPS TFTs. The importance of patterning the amorphous silicon film into separate super-mesa elements prior to FLA crystallization was previously established. The FLA system for this work was a NovaCentrix PulseForge 3300 system, used to crystallize polygons of a-Si with a 100 nm SiO 2 capping layer. The FLA response of densely packed mesa arrays exhibits a proximity effect which impedes the melting of interior mesas, whereas exterior mesas demonstrate a crystallization response consistent with isolated mesas. This comparison is highlighted in Fig. 1 by the pronounced gradient in crystallization morphology. These observations have led to a theory of competing rates between solid-phase and liquid-phase crystallization, hypothesized due to the large difference between the melting points of amorphous and crystalline silicon. The challenge of dopant activation is exacerbated by the need to limit lateral diffusion. Dopants within silicon that has entered a liquid phase will experience dramatically enhanced diffusion, even within the ultra-short pulse duration of the FLA process. The result is a compromised intrinsic channel which limits device scaling. Thus, dopants must be introduced into post-FLA LTPS and activated at glass-compatible temperatures, which is also a requirement for self-aligned devices. Solid-phase dopant activation in FLA-LTPS films has been investigated using furnace annealing and multiple shot FLA exposures at lower intensity. Pre-amorphizing the source/drain regions with electrically inactive species has also been explored. Hydrogen passivation treatments using both plasma and sintering processes have been investigated in efforts to reduce the influence of defect states. Pre-amorphization and passivation processes have yielded promising device characteristics with low series resistance, low leakage current, and high carrier mobility, as shown in Fig. 2. Figure 1

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