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Record W4239075919 · doi:10.22215/etd/2018-13308

Charge-Steering Latches

2018· dissertation· en· W4239075919 on OpenAlexaff
Jacob Pike

Bibliographic record

Venuenot available
Typedissertation
Languageen
FieldEngineering
TopicAdvancements in Semiconductor Devices and Circuit Design
Canadian institutionsCarleton University
Fundersnot available
KeywordsCMOSTransceiverNetwork topologyElectronic engineeringTransient (computer programming)WirelineTopology (electrical circuits)EngineeringElectronic circuitCharge (physics)Electrical engineeringComputer sciencePhysicsTelecommunications

Abstract

fetched live from OpenAlex

Modern wireline transceivers are explored to understand the limitations in their design and how their performance -in terms of speed and power consumptioncan be pushed.This exploration leads to the revelation that charge-steering based transceivers have a high potential.As such, an in-depth transient analysis of the basic charge-steering latch is presented, providing new insight into the operation of chargesteering circuits.This insight is utilized to develop design equations for the basic charge-steering latch.The design equations lead to improvement in charge-steering latch design (lower power consumption, higher swing) when compared to prior art.While prior art focused on charge-steering systems (ie.data converters and SerDes), the focus on individual latch improvement could also improve these systems.Several new charge-steering latch topologies are also proposed.The transient analysis is extended to one of these latches, the charge-steering latch with a clocked cross-coupled pair.New design equations are also presented for this latch.Post-layout simulations of these latches are done in 28nm FD-SOI CMOS and further simulations are performed in 65nm CMOS.The new design equations and latch topologies enable the use of charge-steering latches at 28Gb/s and beyond, at new levels of performance.Power savings of as much as 40% are demonstrated by the new topologies, all other specifications being equal.As data transmission speeds are pushed to as much as 1 terabit per second, single lane transceivers are required which operate at 56Gb/s and beyond.The new charge-steering circuits and design equations can enable a 56Gb/s transceiver when used in a half-rate architecture.First, I would like to acknowledge Dr. Calvin Plett for his supervision of my thesis.His willingness to supervise me almost a year after I started my Masters is very much so appreciated and his expertise of integrated circuits has been extremely valuable in the completion of my thesis.I also appreciate his facilitating my relationship with Ciena Corporation where I had the opportunity to learn from many other experts in integrated circuit design.My manager at Ciena, Dr. Naim Ben-Hamida, has been very graceful in lending me his time, as have others on the Analog Integrated Circuit team, including Dr. Jerry Lam

Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.

How this classification was reachedexpand

Full frame machine prediction

Teacher imitation

Not calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.

metaresearch head score (Codex)0.000
metaresearch head score (Gemma)0.001
Version: metacan-v3-hybrid-931329e0061cValidation status: machine_predicted_unvalidated
Candidate categoriesnone
Consensus categoriesnone
DomainCandidate signal: none · Consensus signal: none
Study designCandidate signal: Bench or experimental · Consensus signal: none
GenreCandidate signal: Empirical · Consensus signal: none
Teacher disagreement score0.007
Threshold uncertainty score0.022

Distilled classifier scores by category (both heads)

CategoryCodexGemma
Metaresearch0.0000.001
Meta-epidemiology (narrow)0.0000.000
Meta-epidemiology (broad)0.0000.000
Bibliometrics0.0000.000
Science and technology studies0.0000.000
Scholarly communication0.0010.001
Open science0.0010.000
Research integrity0.0010.000
Insufficient payload (model declined to judge)0.0070.001

Machine scores (provisional)

The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.

Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.

Opus teacher head0.014
GPT teacher head0.239
Teacher spread0.224 · how far apart the two teachers sit on this one work
Validation statusscore_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from it

Classification

machine, unvalidated

Machine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.

The models applied no category: nothing in the taxonomy fit this work.
Study designBench or experimental
Domainnot available
GenreEmpirical

How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".

Quick stats

Citations1
Published2018
Admission routes1
Has abstractyes

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