Bibliographic record
Abstract
Modern wireline transceivers are explored to understand the limitations in their design and how their performance -in terms of speed and power consumptioncan be pushed. This exploration leads to the revelation that charge-steering based transceivers have a high potential. As such, an in-depth transient analysis of the basic charge-steering latch is presented, providing new insight into the operation of chargesteering circuits. This insight is utilized to develop design equations for the basic charge-steering latch. The design equations lead to improvement in charge-steering latch design (lower power consumption, higher swing) when compared to prior art. While prior art focused on charge-steering systems (ie. data converters and SerDes), the focus on individual latch improvement could also improve these systems. Several new charge-steering latch topologies are also proposed. The transient analysis is extended to one of these latches, the charge-steering latch with a clocked cross-coupled pair. New design equations are also presented for this latch. Post-layout simulations of these latches are done in 28nm FD-SOI CMOS and further simulations are performed in 65nm CMOS. The new design equations and latch topologies enable the use of charge-steering latches at 28Gb/s and beyond, at new levels of performance. Power savings of as much as 40% are demonstrated by the new topologies, all other specifications being equal. As data transmission speeds are pushed to as much as 1 terabit per second, single lane transceivers are required which operate at 56Gb/s and beyond. The new charge-steering circuits and design equations can enable a 56Gb/s transceiver when used in a half-rate architecture.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame distilled prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. Learned from the 10,348 direct Codex labels and 10,348 direct Gemma labels. Candidate is the union of thresholded teacher heads; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels or direct frontier model labels.
Codex and Gemma teacher scores by category
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.003 | 0.001 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one teacher head, not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".