Efficient DEVS Simulations Design on Heterogeneous Platforms

Modeling and Simulation (M&S) has become an essential tool in science and engineering due to its ability to represent problems in various disciplines and conduct scientific explorations. To define solutions based on M&S it is important to have formal definitions for the models. In this way, we can define the models with precision, as well as verify and reuse them. The Discrete Event System Specification (DEVS) formalism provides a theoretical formalism for developing M&S based on discrete events. While we can use DEVS to define models precisely, an issue with M&S is that the simulation of complex problems generally requires a significant number of computations, and this leads to large execution times. In addition, deploying simulations in parallel computers presents an additional challenge, the energy high-performance computers need to operate. To address these issues, we propose a methodology to execute DEVS simulation efficiently in modern parallel computer architectures. Our approach provides a simple and error-free method that improves previous approaches by allowing additional parallelism. We propose novel algorithms aimed for multicore computers, and heterogeneous platforms composed by multicore and GPU architectures in the same system. To evaluate our methodology, we provide an extensive performance analysis over a synthetic benchmark and a real-world problem. Our experimental results show how our approach allows us to accelerate simulations up to 32.9 times. We also analyze the energy consumption required by parallel computers to execute simulations. The amount of energy consumed depends on both the execution time and the power used by the hardware. Power is defined as the amount of energy consumed per unit of time. Our experimental findings demonstrate that while parallel execution consumes more power this can ultimately lead to energy reductions by allowing simulations to complete faster. Finally, we investigated the application of the Dynamic Voltage and Frequency Scaling (DVFS) technique on our parallel algorithms. Our results showed that certain configurations of DVFS can lead to reduced power and energy consumption, however, this comes at the expense of time performance. Overall, our evaluation highlights that the best frequency configuration depends on which metric we try to improve.

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