The design of an SoC-based programmable controller development platform
Bibliographic record
Abstract
This thesis presents the development of the basis for an industrial controller based onSystem-on-Chip FPGA (SoC FPGA) technology as well as its accompanying suite of de-velopment tools. The objective of the project is to design an industrial controller devel-opment platform that can gracefully handle both high-level and low-level functionalities.A demonstration of Hardware-in-the-Loop (HIL) simulation with a graphical interface ona SoC FPGA using open-source software is one of the main pillars of the contributions ofthis thesis. First, a review of the embedded system design methodologies, the basics ofco-processor design, and of development environments is presented. Next, the controllerarchitecture's design process, which has produced multiple prototypes, is shown. The rstprototype uses a decoupled architecture with a separate Central Processing Unit (CPU) andField Programmable Gate Array (FPGA). A PCB demonstrating memory accesses from amicrocontroller has been designed. Another prototype simulates a decoupled architecturecomposed of a powerful ARM core and an FPGA connected by PCI-Express (PCI-e). Themost recent design is one based on SoC FPGA technology. To show the possibilities ofthis platform, a suite of example digital IP cores have been designed and simulated. Fur-thermore, a collection of development tools has been assembled and congured to enabledevelopers to use this platform. In addition to the standard GNU tools, the thesis putsan emphasis on the modication of open-source simulation software to enable developmentwith HIL simulation.
Fetched live from OpenAlex and de-inverted. Abstracts are not stored in this database: the inverted indexes are 8.6 GB of the frame’s 9.3 GB of text, and the host has 13 GB free.
How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.001 | 0.001 |
| Meta-epidemiology (narrow) | 0.001 | 0.001 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.001 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.001 | 0.001 |
| Open science | 0.001 | 0.001 |
| Research integrity | 0.001 | 0.001 |
| Insufficient payload (model declined to judge) | 0.004 | 0.003 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".