Bibliographic record
Abstract
This thesis deals with the design and implementation of low power DSP systems utilizing energy recovery. Implementation of arithmetic units is identified as the key problem in achieving high energy efficiency since conventional arithmetic architectures do not allow efficient energy recovery. For this reason, the thesis focuses on the design of arithmetic units suitable for energy recovery. Based on the finding that non-adiabatic dissipation associated with full-swing signals sets a practical limit for energy efficiency in adiabatic arithmetic circuits, a design strategy is defined by which, the non-adiabatic dissipation is reduced through architectural, rather than circuit optimizations. This is achieved by using arithmetic architectures involving a small number of complex logic gates. In order to enable such architectural design, a circuit technique named OBDDL, allowing reliable and energy efficient operation of complex logic gates, is developed. A class of OBDDL gates called “counter OBDDL” is identified as particularly suitable for design of adiabatic arithmetic units. Superior performance and energy efficiency of OBDDL-based building blocks for arithmetic design, over equivalent circuits implemented using other adiabatic techniques, is verified by circuit simulation. Using the adopted strategy and the developed circuit technique, energy efficient architectures for adiabatic implementation of parallel multipliers and distributed arithmetic architectures are developed. The feasibility and energy efficiency of the proposed adiabatic design style is further verified by several implementations including a single-stage 5 x 5-bit multiplier, a 15 x 15-bit pipelined adiabatic multiplier-accumulator (MAC), an adiabatic RAM and a 72-point adiabatic FFT processor core. The experimental results obtained for each of these implementations suggest that adiabatic DSP design based on the proposed approach results in a significant improvement in energy efficiency over conventional low power design, as well as over competing adiabatic techniques, while allowing high operating speed for DSP applications.
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How this classification was reachedexpand
Full frame machine prediction
Teacher imitationNot calibrated prevalence, not ground truth. Human validation pending. The Gemma side is a direct model label for every work in the frame, read from the title-only record. The Codex side is a classifier learned from the 10,348 direct Codex labels and calibrated to design-weighted sample rates; fields without enough sample support carry no Codex call. Candidate is the union of the two sides; consensus is their intersection. These outputs are machine_predicted_unvalidated and are not human labels.
Distilled classifier scores by category (both heads)
| Category | Codex | Gemma |
|---|---|---|
| Metaresearch | 0.000 | 0.000 |
| Meta-epidemiology (narrow) | 0.000 | 0.000 |
| Meta-epidemiology (broad) | 0.000 | 0.000 |
| Bibliometrics | 0.000 | 0.000 |
| Science and technology studies | 0.000 | 0.000 |
| Scholarly communication | 0.000 | 0.000 |
| Open science | 0.000 | 0.000 |
| Research integrity | 0.000 | 0.000 |
| Insufficient payload (model declined to judge) | 0.003 | 0.001 |
Machine scores (provisional)
The two teacher heads of the student model, read on this work. A score orders the frame for review; it never asserts a category, and the validation status ships verbatim with every row.
Baseline scores from an immature model (maturity gate not passed, 7 training rounds). Scores rank; they never assert a category.
score_only:v0-immature-baseline · verbatim from the scoring run: score_only means the number may rank works, and no category label ships from itClassification
machine, unvalidatedMachine predicted; a candidate call from one source (direct Gemma or distilled Codex), not a consensus.
How this classification was reached, model by model and score by score, is at the end of the page under "How this classification was reached".