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4,299,418 works, Canadian by any of four routes.

Every filter state is a URL; the URL is the query; the query is citable via /q/⟨hash⟩. The page, the API and the export parse the same parameters.

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The current cohort, streamed from the database: every work column, the machine labels, the provisional scores, and the per-row validation status. Exports are capped at 100,000 rows. Mints a permanent /q/ link for this exact query. The same filters always produce the same link, whoever asks.

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Low-power high-performance VLSI design
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Direct Codex and Gemma labels are unvalidated and sparse. Distilled predictions cover the full frame and are also unvalidated. Choose the evidence source explicitly; absence of a direct label is never a negative label.

affaffiliation
fundfunder
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The four routes compose: require the funder route and exclude affiliation to get the funder-only stratum no affiliation-based frame ever sees.

955 results · 1 filter active ·
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20002025
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Machine labels · sparse coverage
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An unlabeled work is unknown, not a negative. Label coverage is reported on every query.
955 works in the cohort · of 4,299,418page 3 of 20

Labels cover 2 of 955 works in this cohort. The rest are unlabeled, which is not a negative label: the label table is sparse today and grows as labeling rounds land.

Distilled predictions cover 955 of 955 works in this cohort. Predictions are machine_predicted_unvalidated teacher distillation outputs. Candidate is the union; consensus is the intersection.

affno abstractunlabeled
Accelerated Stochastic Power Iteration
Peng Xu, Bryan He, Christopher De, Ioannis Mitliagkas, Christopher Ré
2018· article· en· International Conference on Artificial Intelligence and Statistics· Engineering
distilled prediction:candidate · insufficient_payloadconsensus · insufficient_payload
30
citations
affunlabeled
FPGA Design for Timing Yield Under Process Variations
Akhilesh Kumar, Mohab Anis
2009· article· en· IEEE Transactions on Very Large Scale Integration (VLSI) Systems· Engineering
distilled prediction:candidate · metaepi_narrowconsensus · none
24
citations
affunlabeled
A Design Framework for Invertible Logic
Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata +2 more
2020· article· en· IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems· Engineering
distilled prediction:candidate · metaepi_narrowconsensus · none
24
citations
affunlabeled
Smashing the Implementation Records of AES S-box
Arash Reyhani-Masoleh, Mostafa Taha, Doaa Ashmawy
2018· article· en· DOAJ (DOAJ: Directory of Open Access Journals)· Engineering
distilled prediction:candidate · insufficient_payloadconsensus · none
22
citations
affunlabeled
High-speed parallel CRC circuits
Christopher Kennedy, Arash Reyhani-Masoleh
2008· article· en· Engineering
distilled prediction:candidate · insufficient_payloadconsensus · none
21
citations
affunlabeled
Fast Vectorless Power Grid Verification Under an RLC Model
Nahi H. Abdul Ghani, Farid N. Najm
2011· article· en· IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems· Engineering
distilled prediction:candidate · metaepi_narrowconsensus · none
21
citations
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